1. Field
Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same.
2. Description of the Related Art
A complementary metal-oxide semiconductor (CMOS) image sensor is an integrated sensor having a block configured to amplify or process signal in a sensor chip using an active element such as a MOS or CMOS transistor.
In general, a unit pixel of the CMOS image sensor includes one photodiode PD and four NMOS transistors TX, RX, SX, and DX as explained below. The transfer transistor TX transfers photogenerated charges collected by the photodiode PD to a floating diffusion region FD. The reset transistor RX serves to set the potential of a node to a desired value and discharge charges Cpd the photogenerated charges to reset the floating diffusion region FD. The drive transistor DX serves as a source follower buffer amplifier. The select transistor SX performs addressing through a switching operation.
Here, the transfer transistor TX and the reset transistor RX include a native NMOS transistor, and the drive transistor DX and the select transistor SX include a normal NMOS transistor. The reset transistor RX is a transistor for correlated double sampling (CDS).
That is, in each image pixel of the CMOS image sensor, general CMOS elements are used to implement the photodiode and the transistors. Therefore, the existing CMOS process may be applied. Accordingly, an integrated image signal processing and detecting unit may be provided in a block outside the pixel.
FIG. 1 is a cross-sectional view of a conventional CMOS image sensor.
Referring to FIG. 1, a punch-through prevention layer 12 is formed over a substrate 11. An epitaxially-grown silicon epitaxial layer 13 is formed over the punch-through prevention layer 12. An isolation layer 15B is formed. The isolation layer 15B is included in a channel stop region 15A formed from a surface of the silicon epitaxial layer 13. A gate electrode 16 of a transfer transistor TX is formed over the silicon epitaxial layer 13. An N-type diffusion layer 17 is formed in the silicon epitaxial layer 13 to be aligned with one edge of the gate electrode 16. A P-type diffusion layer 18 is formed over the N-type diffusion layer 17 and below the surface of the silicon epitaxial layer 13 while aligned with the one edge of the gate electrode 15.
As a result, a photodiode that includes the N-type diffusion layer 17 and the P-type diffusion layer 18 is formed.
At this time, in order to suppress crosstalk and improve sensitivity, an extended photodiode region 19 is formed below the N-type diffusion layer 17 to overlap a part of the gate electrode 16.
Furthermore, in order to prevent crosstalk between adjacent pixels, a P-type field stop region 14 is formed below the channel stop region 15A in the silicon epitaxial layer 13 to be contacted with the punch-through prevention layer 12. At this time, one side of the P-type field stop region 14 is aligned with a center of the gate electrode 16, and contacted with one side of the extended photodiode region 19.
Furthermore, a floating diffusion region 20 is formed in the P-type field stop region 14 to be substantially aligned with the other side of the gate electrode 16.
However, when the extended photodiode region 19 is formed to suppress crosstalk and improve sensitivity, there are difficulties in forming the extended photodiode region 19 by ion-implanting high concentration N-type impurities. The reason is that a specific dose of photogenerated charges are not normally transferred to the floating diffusion region 20 through a channel of the gate electrode 16 under a limited voltage condition of the gate electrode, thereby causing an image lag. Because a space where a depletion region is to be extended is insufficient, an image lag may occur, and sensing characteristics may be degraded.